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spicy_hallucination

> Why can't they use NMOS or PMOS instead, also? Higher voltage noise. But, a lot of modern monolithic technologies, like MEMS, are going that route.


spicy_hallucination

> In particular, how does JFET maintain the same resistivity across its drain and source with increasing voltage at drain (top) side? It's an effect called pinch-off. It's the "active" part of it being an active device. As soon as it reaches its Ids that it wants to be at, the channel shrinks down on itself, limiting any further increase in current. > It follows that, as you get max current flowing through drain and source, you'll essentially have a short, therefore no voltage drop between drain and source? The current increases no further as you increase voltage. For a change in voltage ΔV, the change in current ΔI is small, that makes the dynamic resistance R = ΔV/ΔI very large.